Differential sense amplifier latches are frequently used in input/output (IO) circuits to latch external input signals with short setup and hold times. The external signals, however, frequently have high common-mode voltages that are not compatible with the power supply voltage levels of the sense amplifier latch for a state-of-the-art 90 nm process. For example, the external signals may have common-mode voltages of 1.125 v for logic voltages 1.5 v and 0.75 v, while the power supply voltage levels of the sense amplifier latch may be 1.1 v and 0 v. As a result, these latches frequently require voltage translator circuits, such as source followers, inserted between them and the external signals to translate external voltages to levels appropriate for the conventional latches. The common-mode input voltage, however, could have such a wide range (e.g., 0.775 v to 1.475 v) that the translator and, therefore, the conventional sense amplifier latch circuits, may not work in all integrated circuit process corners.
If a conventional differential sense amplifier latch is used to directly interface with wide-range common-mode inputs, the input pull-down devices are difficult to implement. As a result, they cannot accept input signals with a small difference and large common-mode voltages, since they are not effective in creating rail voltage differences under such conditions. The result is that the rail voltages of the sense amplifier are driven very low (toward ground) with very little difference between the rails, thus failing to provide reliable operation. As a result, conventional sense amplifier latches require voltage translator circuits to translate input voltages to appropriate levels when input signals with small differences and large common-mode voltages are encountered.
In view of the foregoing, there is a need for an improved sense amplifier latch that is capable of directly interfacing with high common-mode input voltages while working in all integrated circuit process corners.